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SEMTECH
T oday's Results...T omorrow's Vision
Low-Voltage 1:10 Differential ECL/PECL/HSTL Clock Driver
SK100EP111
Preliminary Information
This document contains information on a new product. The parametric information, although not fully characterized, is the result of testing initial devices.
October 4, 1999
Low-Voltage 1:10 Differential ECL/PECL/HSTL Clock Driver
Features
* * * * * * * * 100 ps Part-to-Part Skew 35 ps Output-to-Output Skew Differential Design VBB Output Low Voltage VEE Range of -2.375 to -3.8V for ECL Low Voltage VCC Range of +2.375 to +3.8V for PECL and HSTL 75 K Input Pulldown Resistors ECL/PECL Outputs 32 Lead LQFP Package
Logic Symbol
CLK0 10 0 Q0:9 1 VBB Q0*:9*
Description
The SK100EP111 is a low skew 1-to-10 diffferential driver, designed with clock distribution in mind. It accepts two clock sources into an input multiplexer. The ECL/PECL input signals can be either differential or single-ended if the VBB output is used. HSTL inputs can be used when the EP111 is operating under PECL conditions. The selected signal is fanned out to 10 identical differential outputs. The SK100EP111 is specifically designed, modeled, and produced with low skew as the key goal. Optimal design and layout serve to minimize gate-to-gate skew within a device, and characterization is used to determine process control limits that ensure consistent tpd distributions from lot to lot. The net result is a dependable, guaranteed low skew device. To ensure that the tight skew specification is met, it is necessary that both sides of the differential output are terminated into 50, even if only one side is being used. In most applications, all ten differential pairs will be used and therefore terminated. In the case where fewer than ten pairs are used, it is necessary to terminate at least the output pairs on the same package side as the pair(s) being used on that side in order to maintain minimum skew. Failure to do this will result in small degradations of propagation delay (on the order of 10-20 ps) of the output(s) being used which, while not being catastrophic to most designs, will mean a loss of skew margin. The SK100EP111, as with most other ECL devices, can be operated from a positive VCC supply in PECL mode. This allows the EP111 to be used for high performance clock distribution in +3.3V or +2.5V systems. Designers can take advantage of the EP111's performance to distribute low skew clocks across the backplane or the board. In a PECL environment, series or Thevenin line terminations are typically used as they require no additional power supplies.
CLK0* CLK1 CLK1* CLK_SEL
Pinout
Q3* Q4* Q5* Q6*
17 16 15 14
Q3
Q4
Q5
24
23
22
21
20 19
18
VCC0 Q2* Q2 Q1* Q1 Q0* Q0 VCC0
Q6
25 26 27 28 29 30 31 32 1 2 3 4 5 6 7 8
VCC0 Q7 Q7* Q8 Q8* Q9 Q9* VCC0
SK100EP111
13 12 11 10 9
VCC
CLK0*
VBB
CLK1*
CLK_SEL
CLK0
Pin Names
Pin CLK0, CLK0* CLK1, CKL1* Q0:9, Q0*:9* CLK_SEL VBB Function Differential ECL/PECL Input Pair Differential HSTL Input Pair Differential PECL Outputs Active Clock Select Input VBB Output
Function
CLK_SEL 0 1 Active Input CLK0, CLK0* CLK1, CLK1*
CLK1
VEE
SEMTECH
T oday's Results...T omorrow's Vision
Low-Voltage 1:10 Differential ECL/PECL/HSTL Clock Driver
SK100EP111
ECL DC Characteristics
-40o C Symbol VOH VOL VIH VIL VBB VEE IIH IEE Characteristic Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Output Reference Voltage Power Supply Voltage Input High Current Power Supply Current VEE = -2.375 to -3.8V Common Mode Range Minimum Input Swing VEE + 1.7 500 80 Min -1.140 -1.830 -1.165 -1.810 -1.38 -2.375 -1.475 -1.26 -3.8 150 10 8 VCC 0.3 VEE + 1.7 500 80 Typ -1.005 -1.695 Max -0.880 -1.555 Min -1.080 -1.810 -1.165 -1.810 -1.38 -2.375 0o C Typ -0.955 -1.705 Max -0.880 -1.620 -0.880 -1.475 -1.26 -3.8 150 108 VCC 0.3 VEE + 1.7 500 80 Min -1.080 -1.810 -1.165 -1.810 -1.38 -2.375 25o C Typ Max -0.880 -1.620 -0.880 -1.475 -1.26 -3.8 150 108 VCC 0.3 VEE + 1.7 500 80 Min -1.080 -1.810 -1.165 -1.810 -1.38 -2.375 85o C Typ -0.955 -1.705 Max -0.880 -1.620 -0.880 -1.475 -1.26 -3.8 150 117 VCC 0.3 Unit V V V V V V A mA V mV
VCMR VPP
HSTL DC Characteristics
-40oC Symbol VCMR VPP Characteristic Common Mode Range Minimum Input Swing Min VEE + 0.9 500 Typ Max VCC 1.1 Min VEE + 0.9 500 0oC Typ Max VCC 1.1 Min VEE + 0.9 500 25oC Typ Max VCC 1.1 Min VEE + 0.9 500 85oC Typ Max VCC 1.1 Unit V mV
SEMTECH
T oday's Results...T omorrow's Vision
Low-Voltage 1:10 Differential ECL/PECL/HSTL Clock Driver
SK100EP111
PECL DC Characteristics
-40o C Symbol VOH VOL VIH VIL VBB VEE IIH I EE Characteristic Output HIGH Voltage (Note 1) Output LOW Voltage (Note 1) Input HIGH Voltage (Note 1) Input LOW Voltage (Note 1) Output Reference Voltage (Note 1) Power Supply Voltage Input HIGH Current Power Supply Current VCC = +2.375 to +3.8V Common Mode Range Minimum Input Swing VEE + 1.7 500 60 Min 2.160 1.470 2.135 1.490 1.92 2.375 Typ 2.295 Max 2.420 1.750 2.420 1.825 2.04 3.8 150 70 VCC 0.3 VEE + 1.7 500 70 Min 2.220 1.490 2.135 1.490 1.92 2.375 0o C Typ Max 2.420 1.680 2.420 1.825 2.04 3.8 150 80 VCC 0.3 VEE + 1.7 500 70 Min 2.220 1.490 2.135 1.490 1.92 2.375 25o C Typ Max 2.420 1.680 2.420 1.825 2.04 3.8 150 80 VCC 0.3 VEE + 1.7 500 80 Min 2.220 1.490 2.135 1.490 1.92 2.375 85o C Typ 2.345 1.595 Max 2.420 1.680 2.420 1.825 2.04 3.8 150 117 VCC 0.3 Unit V V V V V V A mA V mV
VCMR VPP
Note 1: These values are for VCC = 3.3V. Level Specifications will vary 1:1 withVCC.
AC Characteristics (VEE = -2.375V to -3.8V; VCC = VCC0 = GND)
-40oC Symbol tPLH tPHL Characteristic ECL/PECL Prop Delay to Output HSTL Prop Delay to Output Within-Device Skew Part-to-Part Skew fmax tr , tf Max Input Frequency Output Rise/Fall Time 200 Min 310 390 340 580 Typ 380 440 415 610 15 100 1500 600 200 Max 450 480 485 630 30 145 Min 350 410 380 620 0oC Typ 415 460 450 650 15 100 1500 600 200 Max 475 500 510 670 30 130 Min 375 430 410 640 25oC Typ 445 480 480 670 15 100 1500 600 200 Max 510 520 545 700 30 135 Min 480 460 520 670 85oC Typ 575 550 615 700 15 100 1500 600 Max 680 550 720 730 30 150 Unit ps ps ps ps ps ps MHz ps
tskew
SEMTECH
T oday's Results...T omorrow's Vision
Low-Voltage 1:10 Differential ECL/PECL/HSTL Clock Driver
SK100EP111
Package Information
A, B A1, B1
32 25
4X 0.20 (0.008) AB T-U Z
1
24
-T, U, Z - S, V S1,V1
8
17
9
16
SEE DETAIL "Y"
SEE DETAIL "AD" G -AB- -AC- 0.10 (0.004) AC
NOTES: 1. Dimensioning and tolerancing per ANSI Y14.5M, 1982. 2. Controlling Dimension: Millimeter 3. Datum Plane -AB- is located at bottom of lead and is coincident with the lead where the lead exits the plastic body at the bottom of the parting line. 4. Datums -T-, -U-, and -Z- to be determined at Datum Plane -AB-. 5. Dimensions S and V to be determined at Seating Plane -AC-. 6. Dimensions A and B do not include mold protrusion. Allowable protrusion is 0.250 (0.010) per side. Dimensions A and B do not include mold mismatch and are determined at Datum Plane -AB-. 7. Dimension D does not include Dambar protrusion. Dambar protrusion shall not cause the D dimension to exceed 0.520 (0.020). 8. Minimum solder plate thickness shall be 0.0075 (0.0003). 9. Exact shape of each corner may vary from depiction.
MILLIMETERS INCHES
MIN MAX
8x M
DIM
R
MIN
MAX
A A1
C E
7.000 BSC 3.500 BSC 7.000 BSC 3.500 BSC 1.400 0.300 1.350 0.300 1.600 0.450 1.450 0.400
0.276 BSC 0.138 BSC 0.276 BSC 0.138 BSC 0.055 0.012 0.053 0.012 0.063 0.018 0.057 0.016
B B1 C
W H X K Q
0.250 (0.010) GAUGE PLANE
D E
DETAIL AD
-T-, -U-, -Z-
AE P
AE
DETAIL Y
,, ,, , ,, ,, ,, ,
Base Metal
F G H J K M N P Q R S S1 V V1 W X
0.800 BSC 0.050 0.090 0.500 0.150 0.200 0.700
0.031 BSC 0.002 0.004 0.020 0.006 0.008 0.028
12o REF 0.090 0.160
12o REF 0.004 0.006
N
0.400 BSC 1o 0.150 5o 0.250
0.016 BSC 1o 0.006 5o 0.010
F
D
9.000 BSC 4.500 BSC 9.000 BSC 4.500 BSC 0.200 REF 1.000 REF
0.354 BSC 0.177 BSC 0.354 BSC 0.177 BSC 0.008 REF 0.039 REF
N
0.20 (0.008) M AC T-U Z
SECTION AE

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